module COUNTER (clk, reset,dis_seg,dis_led);
   input clk;
   input reset;

   output reg [6:0] dis_seg;
   output reg [8:0] dis_led;
   
   reg realclock;
   reg [28:0] q1;
   reg [3:0] realq;

   always @(posedge clk or negedge reset) begin
      if (!reset)
        begin
           q1 <= 0;
           realclock <= 0;
        end
      else
        begin
        if (q1 == 28'h2faf080)
            //if (q1 == 28'h0000002)
           begin
              realclock <= 1;
              q1 <= 0;
           end
        else
           begin
              realclock <= 0;
              q1 <= q1 + 1;
           end
        end
    end

   always @(posedge realclock or negedge reset) begin
      if (!reset) 
            begin
                realq <= 0;     
            end        
      else
            begin
            if (realq == 10)
                begin
                    realq <= 0;    
                end     
            else
                begin
                realq <= realq + 1;
                end 
        end
   end

   DISPSEG DISPSEG (clk, realq,dis_seg);
   DISPLED DISPLED (clk, realq,dis_led);

endmodule

module DISPSEG (clk,realq,dis_seg);
   input clk;
   input [3:0] realq;
   output reg [6:0] dis_seg;   

always @(posedge clk) begin
   case(realq)
      //0 : dis_seg <= 6'b1111110;
      //1 : dis_seg <= 6'b0110000;
      //2 : dis_seg <= 6'b1101101;
      //3 : dis_seg <= 6'b1111001;
      //4 : dis_seg <= 6'b0110011;
      //5 : dis_seg <= 6'b1011011;
      //6 : dis_seg <= 6'b1011111;
      //7 : dis_seg <= 6'b1110000;
      //8 : dis_seg <= 6'b1111111;
      //9 : dis_seg <= 6'b1111011;
      //default : dis_seg <= 6'b1111110;
      0 : dis_seg <= 7'b0000001;
      1 : dis_seg <= 7'b1001111;
      2 : dis_seg <= 7'b0010010;
      3 : dis_seg <= 7'b0000110;
      4 : dis_seg <= 7'b1001100;
      5 : dis_seg <= 7'b0100100;
      6 : dis_seg <= 7'b0100000;
      7 : dis_seg <= 7'b0001111;
      8 : dis_seg <= 7'b0000000;
      9 : dis_seg <= 7'b0000100;
      default : dis_seg <= 7'b1111110;
   endcase
end
endmodule

module DISPLED (clk,realq,dis_led);
   input clk;
   input [3:0] realq;
   output reg [8:0] dis_led;

always @(posedge clk) begin
   case(realq)
      0 : dis_led <= 9'b000000000;
      1 : dis_led <= 9'b000000001;
      2 : dis_led <= 9'b000000011;
      3 : dis_led <= 9'b000000111;
      4 : dis_led <= 9'b000001111;
      5 : dis_led <= 9'b000011111;
      6 : dis_led <= 9'b000111111;
      7 : dis_led <= 9'b001111111;
      8 : dis_led <= 9'b011111111;
      9 : dis_led <= 9'b111111111;
      default : dis_led <= 9'b000111000;
   endcase
end
endmodule