프로그램을 합성한뒤 핀셋을 하고 보드에 넣고 시물레이션을 하게되면
1분이 표시되는 카운터 소스입니다.
0~5 대의 10초 단위와 0~9대의 1초단위, 0~9대의 1over10초 단위, 0~9대의 1over100초 단위가 표시되며,
LED가 순차 점등됩니다.
닫기 ㅋ Code Type : C
module COUNTER (clk, reset, dis_seg, dis_seg2, dis_seg3, dis_seg4, dis_led);
input clk;
input reset;
output reg [6:0] dis_seg;
output reg [6:0] dis_seg2;
output reg [6:0] dis_seg3;
output reg [6:0] dis_seg4;
output reg [8:0] dis_led;
reg realclock;
reg realclock2;
reg realclock3;
reg realclock4;
reg [28:0] q1;
reg [30:0] q2;
reg [28:0] q3;
reg [28:0] q4;
reg [3:0] realq;
reg [3:0] realq2;
reg [3:0] realq3;
reg [3:0] realq4;
always @(posedge clk or negedge reset) begin
if (!reset)
begin
q1 <= 0;
realclock <= 0;
end
else
begin
if (q1 == 28'h2faf080)
begin
realclock <= 1;
q1 <= 0;
end
else
begin
realclock <= 0;
q1 <= q1 + 1;
end
end
end
always @(posedge clk or negedge reset) begin
if (!reset)
begin
q2 <= 0;
realclock2 <= 0;
end
else
begin
if (q2 == 30'h1DCD6500)
begin
realclock2 <= 1;
q2 <= 0;
end
else
begin
realclock2 <= 0;
q2 <= q2 + 1;
end
end
end
always @(posedge clk or negedge reset) begin
if (!reset)
begin
q3 <= 0;
realclock3 <= 0;
end
else
begin
if (q3 == 28'h4C4B40)
begin
realclock3 <= 1;
q3 <= 0;
end
else
begin
realclock3 <= 0;
q3 <= q3 + 1;
end
end
end
always @(posedge clk or negedge reset) begin
if (!reset)
begin
q4 <= 0;
realclock4 <= 0;
end
else
begin
if (q4 == 28'h7A120)
begin
realclock4 <= 1;
q4 <= 0;
end
else
begin
realclock4 <= 0;
q4 <= q4 + 1;
end
end
end
always @(posedge realclock or negedge reset) begin
if (!reset)
begin
realq <= 0;
end
else
begin
if (realq == 9)
begin
realq <= 0;
end
else
begin
realq <= realq + 1;
end
end
end
always @(posedge realclock2 or negedge reset) begin
if (!reset)
begin
realq2 <= 0;
end
else
begin
if (realq2 == 5)
begin
realq2 <= 0;
end
else
begin
realq2 <= realq2 + 1;
end
end
end
always @(posedge realclock3 or negedge reset) begin
if (!reset)
begin
realq3 <= 0;
end
else
begin
if (realq3 == 9)
begin
realq3 <= 0;
end
else
begin
realq3 <= realq3 + 1;
end
end
end
always @(posedge realclock4 or negedge reset) begin
if (!reset)
begin
realq4 <= 0;
end
else
begin
if (realq4 == 9)
begin
realq4 <= 0;
end
else
begin
realq4 <= realq4 + 1;
end
end
end
DISPSEG DISPSEG (clk, realq,dis_seg);
DISPSEG DISPSEG2 (clk, realq2,dis_seg2);
DISPSEG DISPSEG3 (clk, realq3,dis_seg3);
DISPSEG DISPSEG4 (clk, realq4,dis_seg4);
DISPLED DISPLED (clk, realq,dis_led);
endmodule
module DISPSEG (clk,realq,dis_seg);
input clk;
input [3:0] realq;
output reg [6:0] dis_seg;
always @(posedge clk) begin
case(realq)
0 : dis_seg <= 7'b0000001;
1 : dis_seg <= 7'b1001111;
2 : dis_seg <= 7'b0010010;
3 : dis_seg <= 7'b0000110;
4 : dis_seg <= 7'b1001100;
5 : dis_seg <= 7'b0100100;
6 : dis_seg <= 7'b0100000;
7 : dis_seg <= 7'b0001111;
8 : dis_seg <= 7'b0000000;
9 : dis_seg <= 7'b0000100;
endcase
end
endmodule
module DISPLED (clk,realq,dis_led);
input clk;
input [3:0] realq;
output reg [8:0] dis_led;
always @(posedge clk) begin
case(realq)
0 : dis_led <= 9'b000000000;
1 : dis_led <= 9'b000000001;
2 : dis_led <= 9'b000000011;
3 : dis_led <= 9'b000000111;
4 : dis_led <= 9'b000001111;
5 : dis_led <= 9'b000011111;
6 : dis_led <= 9'b000111111;
7 : dis_led <= 9'b001111111;
8 : dis_led <= 9'b011111111;
9 : dis_led <= 9'b111111111;
endcase
end
endmodule
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