small MIPS에서 사용하게될 RegisterFiles 입니다.
32-bit ALU와 마찬가지로 상업적 이용은 불가하며, 주석은 모두 삭제 하였습니다.
시물레이션 결과는 아래와 같습니다. ( Functional Simulation 입니다. )
닫기 Code Type : VerilogHDL
/*
-----------------------------------------------------------------------
Title : 32-bit Register files
File : alu_32bit.v
-----------------------------------------------------------------------
Author : Oh, Hyung-Tak
Organization : Kwangwoon university
Created : 2007.4.30
Last update : 2007.5.15
Platform : WINDOWS XP
Simulators : Quartus II 6.0
Synthesizers : Quartus II 6.0
Target : Cyclone II:AUTO
-----------------------------------------------------------------------
Descriptions : registor files를 작성한다.
Revisions Number : 1
Version : 1.0
Date of change :
Modifier : Oh, Hyung-Tak ( ohyung@ohyung.com )
Description of change :
-------------------------------------------------------------------------
*/
module reg_files (clk, rst_n, write, read_reg1, read_reg2, write_reg, write_data, read_data1, read_data2);
input clk, rst_n, write;
input [04:0] read_reg1, read_reg2, write_reg;
input [31:0] write_data;
output [31:0] read_data1, read_data2;
wire [31:0] we;
wire [31:0] data_out00, data_out01, data_out02, data_out03, data_out04;
wire [31:0] data_out05, data_out06, data_out07, data_out08, data_out09;
wire [31:0] data_out10, data_out11, data_out12, data_out13, data_out14;
wire [31:0] data_out15, data_out16, data_out17, data_out18, data_out19;
wire [31:0] data_out20, data_out21, data_out22, data_out23, data_out24;
wire [31:0] data_out25, data_out26, data_out27, data_out28, data_out29;
wire [31:0] data_out30, data_out31;
decoder_32to1 data_out0 (write_reg[04:0], we[31:0]);
reg_32bit u0 (clk, rst_n, we[0]&write, write_data, data_out00);
reg_32bit u1 (clk, rst_n, we[1]&write, write_data, data_out01);
reg_32bit u2 (clk, rst_n, we[2]&write, write_data, data_out02);
reg_32bit u3 (clk, rst_n, we[3]&write, write_data, data_out03);
reg_32bit u4 (clk, rst_n, we[4]&write, write_data, data_out04);
reg_32bit u5 (clk, rst_n, we[5]&write, write_data, data_out05);
reg_32bit u6 (clk, rst_n, we[6]&write, write_data, data_out06);
reg_32bit u7 (clk, rst_n, we[7]&write, write_data, data_out07);
reg_32bit u8 (clk, rst_n, we[8]&write, write_data, data_out08);
reg_32bit u9 (clk, rst_n, we[9]&write, write_data, data_out09);
reg_32bit u10 (clk, rst_n, we[10]&write, write_data, data_out10);
reg_32bit u11 (clk, rst_n, we[11]&write, write_data, data_out11);
reg_32bit u12 (clk, rst_n, we[12]&write, write_data, data_out12);
reg_32bit u13 (clk, rst_n, we[13]&write, write_data, data_out13);
reg_32bit u14 (clk, rst_n, we[14]&write, write_data, data_out14);
reg_32bit u15 (clk, rst_n, we[15]&write, write_data, data_out15);
reg_32bit u16 (clk, rst_n, we[16]&write, write_data, data_out16);
reg_32bit u17 (clk, rst_n, we[17]&write, write_data, data_out17);
reg_32bit u18 (clk, rst_n, we[18]&write, write_data, data_out18);
reg_32bit u19 (clk, rst_n, we[19]&write, write_data, data_out19);
reg_32bit u20 (clk, rst_n, we[20]&write, write_data, data_out20);
reg_32bit u21 (clk, rst_n, we[21]&write, write_data, data_out21);
reg_32bit u22 (clk, rst_n, we[22]&write, write_data, data_out22);
reg_32bit u23 (clk, rst_n, we[23]&write, write_data, data_out23);
reg_32bit u24 (clk, rst_n, we[24]&write, write_data, data_out24);
reg_32bit u25 (clk, rst_n, we[25]&write, write_data, data_out25);
reg_32bit u26 (clk, rst_n, we[26]&write, write_data, data_out26);
reg_32bit u27 (clk, rst_n, we[27]&write, write_data, data_out27);
reg_32bit u28 (clk, rst_n, we[28]&write, write_data, data_out28);
reg_32bit u29 (clk, rst_n, we[29]&write, write_data, data_out29);
reg_32bit u30 (clk, rst_n, we[30]&write, write_data, data_out30);
reg_32bit u31 (clk, rst_n, we[31]&write, write_data, data_out31);
mux32bit_32to1 m0 ( data_out00, data_out01, data_out02, data_out03,
data_out04, data_out05, data_out06, data_out07,
data_out08, data_out09, data_out10, data_out11,
data_out12, data_out13, data_out14, data_out15,
data_out16, data_out17, data_out18, data_out19,
data_out20, data_out21, data_out22, data_out23,
data_out24, data_out25, data_out26, data_out27,
data_out28, data_out29, data_out30, data_out31,
read_reg1, read_data1);
mux32bit_32to1 m2 ( data_out00, data_out01, data_out02, data_out03,
data_out04, data_out05, data_out06, data_out07,
data_out08, data_out09, data_out10, data_out11,
data_out12, data_out13, data_out14, data_out15,
data_out16, data_out17, data_out18, data_out19,
data_out20, data_out21, data_out22, data_out23,
data_out24, data_out25, data_out26, data_out27,
data_out28, data_out29, data_out30, data_out31,
read_reg2, read_data2);
endmodule
/* n-to-1 decoder */
module decoder_32to1 (reg_number, out_we);
input [4:0] reg_number;
output [31:0] out_we;
reg [31:0] out_we;
always @ (reg_number)
begin
case (reg_number)
0 : out_we = 32'h00000001;
1 : out_we = 32'h00000002;
2 : out_we = 32'h00000004;
3 : out_we = 32'h00000008;
4 : out_we = 32'h00000010;
5 : out_we = 32'h00000020;
6 : out_we = 32'h00000040;
7 : out_we = 32'h00000080;
8 : out_we = 32'h00000100;
9 : out_we = 32'h00000200;
10 : out_we = 32'h00000400;
11 : out_we = 32'h00000800;
12 : out_we = 32'h00001000;
13 : out_we = 32'h00002000;
14 : out_we = 32'h00004000;
15 : out_we = 32'h00008000;
16 : out_we = 32'h00010000;
17 : out_we = 32'h00020000;
18 : out_we = 32'h00040000;
19 : out_we = 32'h00080000;
20 : out_we = 32'h00100000;
21 : out_we = 32'h00200000;
22 : out_we = 32'h00400000;
23 : out_we = 32'h00800000;
24 : out_we = 32'h01000000;
25 : out_we = 32'h02000000;
26 : out_we = 32'h04000000;
27 : out_we = 32'h08000000;
28 : out_we = 32'h10000000;
29 : out_we = 32'h20000000;
30 : out_we = 32'h40000000;
31 : out_we = 32'h80000000;
default : out_we = 32'h00000000;
endcase
end
endmodule
/* 32 bit register */
module reg_32bit (clk, rst_n, we, data_in, data_out);
input clk, rst_n, we;
input [31:0] data_in;
output [31:0] data_out;
reg [31:0] data_out;
always @ (posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
begin
data_out = 32'b00000000000000000000000000000000;
end
else if (we == 1'b1)
begin
data_out = data_in;
end
end
endmodule
/* 32bit 32 to 1 mux */
module mux32bit_32to1( data_out00, data_out01, data_out02, data_out03,
data_out04, data_out05, data_out06, data_out07,
data_out08, data_out09, data_out10, data_out11,
data_out12, data_out13, data_out14, data_out15,
data_out16, data_out17, data_out18, data_out19,
data_out20, data_out21, data_out22, data_out23,
data_out24, data_out25, data_out26, data_out27,
data_out28, data_out29, data_out30, data_out31,
addr_in, mux_out);
input [4:0] addr_in;
input [31:0] data_out00, data_out01, data_out02, data_out03, data_out04;
input [31:0] data_out05, data_out06, data_out07, data_out08, data_out09;
input [31:0] data_out10, data_out11, data_out12, data_out13, data_out14;
input [31:0] data_out15, data_out16, data_out17, data_out18, data_out19;
input [31:0] data_out20, data_out21, data_out22, data_out23, data_out24;
input [31:0] data_out25, data_out26, data_out27, data_out28, data_out29;
input [31:0] data_out30, data_out31;
output [31:0] mux_out;
reg [31:0] mux_out;
always @ (addr_in or data_out00 or data_out01 or data_out02 or data_out03
or data_out04 or data_out05 or data_out06 or data_out07
or data_out08 or data_out09 or data_out10 or data_out11
or data_out12 or data_out13 or data_out14 or data_out15
or data_out16 or data_out17 or data_out18 or data_out19
or data_out20 or data_out21 or data_out22 or data_out23
or data_out24 or data_out25 or data_out26 or data_out27
or data_out28 or data_out29 or data_out30 or data_out11)
begin
case (addr_in)
0 : mux_out = data_out00;
1 : mux_out = data_out01;
2 : mux_out = data_out02;
3 : mux_out = data_out03;
4 : mux_out = data_out04;
5 : mux_out = data_out05;
6 : mux_out = data_out06;
7 : mux_out = data_out07;
8 : mux_out = data_out08;
9 : mux_out = data_out09;
10 : mux_out = data_out10;
11 : mux_out = data_out11;
12 : mux_out = data_out12;
13 : mux_out = data_out13;
14 : mux_out = data_out14;
15 : mux_out = data_out15;
16 : mux_out = data_out16;
17 : mux_out = data_out17;
18 : mux_out = data_out18;
19 : mux_out = data_out19;
20 : mux_out = data_out20;
21 : mux_out = data_out21;
22 : mux_out = data_out22;
23 : mux_out = data_out23;
24 : mux_out = data_out24;
25 : mux_out = data_out25;
26 : mux_out = data_out26;
27 : mux_out = data_out27;
28 : mux_out = data_out28;
29 : mux_out = data_out29;
30 : mux_out = data_out30;
31 : mux_out = data_out31;
default : mux_out = 0;
endcase
end
endmodule
닫기