아... 빨리 끝날줄 알았건만....
계속 에러 발생... 이번주 내로 끝내고 방학때까지 놀라고 했건만 ㅜㅜ
난.. 왜 이래.. 만날 ㅜㅜ
동작만 되면 3학년때는 간판을 만드는거다! -.-;
닫기
module COUNTER (clk, reset, dis_seg, dis_led);
input clk;
input reset;
output reg [7:0] dis_seg;
output reg [9:0] dis_led;
reg realclock;
reg [28:0] q1;
reg [3:0] realq;
always @(posedge clk or negedge reset) begin // 상승에서 동작합니다.
if (!reset) // 리셋 상황의 경우
begin
q1 <= 0; // 리셋이 되면 q가 0이 됩니다.
realclock <= 0;
end
else //리셋이 아닐때의 경우
begin
// 리셋 상황이 아니라면 q에 1씩 더해집니다.
if (q1 == 28'h2faf080)
begin
realclock <= 1;
q1 <= 0;
end
else
begin
realclock <= 0;
q1 <= q1 + 1;
end
end
end
always @(posedge realclock or negedge reset) begin // 상승에서 동작함
if (!reset) realq <= 0;
else if (realq == 10) realq <= 0;
else realq <= realq + 1;
end
// 표시부분 SEGMENT와 LED
always @(posedge realclock or negedge reset) begin
DISPSEG DISPSEG (clk, realq, dis_seg);
DISPLED DISPLED (clk, realq, dis_led);
end
endmodule
module DISPSEG (clk,segq,dis_seg);
input clk;
input segq;
output reg [7:0] dis_seg;
always @(posedge clk) begin
case(segq)
0 : dis_seg <= 7'b1111110;
1 : dis_seg <= 7'b0110000;
2 : dis_seg <= 7'b1101101;
3 : dis_seg <= 7'b1111001;
4 : dis_seg <= 7'b0110011;
5 : dis_seg <= 7'b1011011;
6 : dis_seg <= 7'b1011111;
7 : dis_seg <= 7'b1110000;
8 : dis_seg <= 7'b1111111;
9 : dis_seg <= 7'b1111011;
default : dis_seg <= 7'b1111110;
endcase
end
endmodule
module DISPLED (clk,ledq,dis_led);
input clk;
input ledq;
output reg [9:0] dis_led;
always @(posedge clk) begin
case(ledq)
0 : dis_led <= 10'b000000000;
1 : dis_led <= 10'b000000001;
2 : dis_led <= 10'b000000011;
3 : dis_led <= 10'b000000111;
4 : dis_led <= 10'b000001111;
5 : dis_led <= 10'b000011111;
6 : dis_led <= 10'b000111111;
7 : dis_led <= 10'b001111111;
8 : dis_led <= 10'b011111111;
9 : dis_led <= 10'b111111111;
default : dis_led <= 10'b000000000;
endcase
end
endmodule
닫기 젠장 module COUNTER (clk, reset, dis_seg, dis_led);
input clk;
input reset;
output reg [7:0] dis_seg;
output reg [9:0] dis_led;
reg realclock;
reg [28:0] q1;
reg [3:0] realq;
always @(posedge clk or negedge reset) begin
if (!reset)
begin
q1 <= 0;
realclock <= 0;
end
else
begin
if (q1 == 28'h2faf080)
begin
realclock <= 1;
q1 <= 0;
end
else
begin
realclock <= 0;
q1 <= q1 + 1;
end
end
end
always @(posedge realclock or negedge reset) begin
if (!reset) realq <= 0;
else if (realq == 10) realq <= 0;
else realq <= realq + 1;
end
DISPSEG DISPSEG (clk, realq);
DISPLED DISPLED (clk, realq);
endmodule
module DISPSEG (clk,segq,dis_seg);
input clk;
input segq;
output reg [7:0] dis_seg;
always @(posedge clk) begin
case(segq)
0 : dis_seg <= 7'b1111110;
1 : dis_seg <= 7'b0110000;
2 : dis_seg <= 7'b1101101;
3 : dis_seg <= 7'b1111001;
4 : dis_seg <= 7'b0110011;
5 : dis_seg <= 7'b1011011;
6 : dis_seg <= 7'b1011111;
7 : dis_seg <= 7'b1110000;
8 : dis_seg <= 7'b1111111;
9 : dis_seg <= 7'b1111011;
default : dis_seg <= 7'b1111110;
endcase
end
endmodule
module DISPLED (clk,ledq,dis_led);
input clk;
input ledq;
output reg [9:0] dis_led;
always @(posedge clk) begin
case(ledq)
0 : dis_led <= 10'b000000000;
1 : dis_led <= 10'b000000001;
2 : dis_led <= 10'b000000011;
3 : dis_led <= 10'b000000111;
4 : dis_led <= 10'b000001111;
5 : dis_led <= 10'b000011111;
6 : dis_led <= 10'b000111111;
7 : dis_led <= 10'b001111111;
8 : dis_led <= 10'b011111111;
9 : dis_led <= 10'b111111111;
default : dis_led <= 10'b000000000;
endcase
end
endmodule
젠장